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Power System Functional Safety Trainee - diákmunka
- Mind-Diák Szövetkezet 4,6
- Hibrid • Budapest XIII.
- Br. 2 400 Ft/óra bér
- Diákmunka • Részmunkaidő
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Nem kell tapasztalat • Angol felsőfok
Főbb feladatok- Contribution in development of concepts and requirements for functional safety rated power supply systems
- Development codes for efficient implementation of methods
- Testing new methods
- Analyse of functional safety concepts
- Analyse measurement results
- Documentation of methods and work
Március 18. -
Experienced Verification Engineer - System IP
- ARM Hungary Kft.
- Hibrid • Budapest
- Teljes munkaidő
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1-3 év tapasztalat • Angol középfok
Főbb feladatokContribute to System IP microarchitecture specification and design Contribute in SystemVerilog, C and C++ to verification, modelling and debug to achieve required quality levels (SystemVerilog/UVM, C, C++, scripting) Propose and prototype new ways and define methodologies to reach goals more...
Március 28. -
Intern, System IP Engineering
- ARM Hungary Kft.
- Hibrid • Budapest
- Teljes munkaidő
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Nem kell tapasztalat • Nem kell nyelvtudás
Főbb feladatokContribute in SystemVerilog RTL verification and debug; formal bring-up of non-trivial IP blocks to achieve required quality levels (SystemVerilog/UVM, Formal, scripting) Work closely with engineers across design, performance modelling, validation, and implementation to meet all functional...
Március 02. -
- Teljes munkaidő
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Nem kell tapasztalat • Angol középfok
Főbb feladatokLead micro architecture and RTL implementation for SoC design Be responsible for the micro-architecture and RTL design of a sophisticated digital subsystem or IP integration into SoC design Translate system requirements into clean, scalable RTL micro architectures including Interface definition,...
Március 03. -
Graduate Engineer, System IP Engineering
- ARM Hungary Kft.
- Hibrid • Budapest
- Teljes munkaidő
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Windows
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Nem kell tapasztalat • Nem kell nyelvtudás
Főbb feladatokBe involved in System IP microarchitecture specification and design Participate in SystemVerilog RTL verification and debug; formal bring-up of non-trivial IP blocks to achieve required quality levels (SystemVerilog/UVM, Formal, scripting) Work closely with engineers across design, performance...
Március 13.
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Open
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Mérnök
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Elektromérnök
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Budapest