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Contribute in SystemVerilog RTL verification and debug; formal bring-up of non-trivial IP blocks to achieve required quality levels (SystemVerilog/UVM, Formal, scripting) Work closely with engineers across design, performance modelling, validation, and implementation to meet all functional...

Lead micro architecture and RTL implementation for SoC design Make independent design decisions and set technical standards for correctness, scalability, and robustness Be responsible for micro-architecture and RTL design of a sophisticated digital subsystem or IP integration into SoC design...