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Be involved in System IP microarchitecture specification and design Participate in SystemVerilog RTL verification and debug; formal bring-up of non-trivial IP blocks to achieve required quality levels (SystemVerilog/UVM, Formal, scripting) Work closely with engineers across design, performance...

Design, prototype, and refine LLM based features over large document sets Orchestrate multi step, agentic workflows and tool calling (including MCP servers and other integrations) so LLMs can take meaningful actions, not just generate text Define evaluation frameworks, experiments, and metrics to...