Internship állás, munka

Contribute in SystemVerilog RTL verification and debug; formal bring-up of non-trivial IP blocks to achieve required quality levels (SystemVerilog/UVM, Formal, scripting) Work closely with engineers across design, performance modelling, validation, and implementation to meet all functional...

• Support the team in designing and developing an internal dashboard to visualize real-world data from diabetes care
• Explore, define, and implement selected dashboard use cases; actively contribute to deciding which use cases provide the most value