Design állások XVI. kerületben (elektromérnök)

Understanding the specification of the target IP to develop and write the RTL Writing, defining and documenting the micro architecture of the IP or the sub system Implement the micro architecture in RTL following the ARM flow standard Develop robust design with high quality using ARM flow checks...

Understanding the specification of the target IP to develop and write the RTL Writing, defining and documenting the micro architecture of the IP or the sub system Implement the micro architecture in RTL following the ARM flow standard Develop robust design with high quality using ARM flow checks...

Lead micro architecture and RTL implementation for SoC design Make independent design decisions and set technical standards for correctness, scalability, and robustness Be responsible for micro-architecture and RTL design of a sophisticated digital subsystem or IP integration into SoC design...

Be involved in the design process of SoCs by integrating the latest Arm IP products while ensuring correct functional behaviour. Develop RTL code using System Verilog. Run EDA tools to check the design and analyze results. Identify and fix bugs. Work directly with engineers across the company to...

Design and develop Arm’s SoC architecture based on Arm product IP and system architecture to meet the requirements of best-in-class compute across our market segments. Work proactively across Arm’s architecture and core technology teams to ensure a roadmap of architecture platforms and technology...

Design and develop Arm’s SoC architecture based on Arm product IP and system architecture to meet the requirements of best-in-class compute across our market segments. Work proactively across Arm’s architecture and core technology teams to ensure a roadmap of architecture platforms and technology...

Contribute in SystemVerilog RTL verification and debug; formal bring-up of non-trivial IP blocks to achieve required quality levels (SystemVerilog/UVM, Formal, scripting) Work closely with engineers across design, performance modelling, validation, and implementation to meet all functional...

Be involved in System IP microarchitecture specification and design Participate in SystemVerilog RTL verification and debug; formal bring-up of non-trivial IP blocks to achieve required quality levels (SystemVerilog/UVM, Formal, scripting) Work closely with engineers across design, performance...