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Contribute in SystemVerilog RTL verification and debug; formal bring-up of non-trivial IP blocks to achieve required quality levels (SystemVerilog/UVM, Formal, scripting) Work closely with engineers across design, performance modelling, validation, and implementation to meet all functional...

Be involved in System IP microarchitecture specification and design Participate in SystemVerilog RTL verification and debug; formal bring-up of non-trivial IP blocks to achieve required quality levels (SystemVerilog/UVM, Formal, scripting) Work closely with engineers across design, performance...

Develop and execute test plans and verification methodologies for SoC-level designs. Complete functional verification to the required quality standards and schedules. Collaborate with project leads and management on planning, scheduling, and quality checkpoints. Ensure progress and quality of SoC...