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Be involved in System IP microarchitecture specification and design Participate in SystemVerilog RTL verification and debug; formal bring-up of non-trivial IP blocks to achieve required quality levels (SystemVerilog/UVM, Formal, scripting) Work closely with engineers across design, performance...

Contribute in SystemVerilog RTL verification and debug; formal bring-up of non-trivial IP blocks to achieve required quality levels (SystemVerilog/UVM, Formal, scripting) Work closely with engineers across design, performance modelling, validation, and implementation to meet all functional...

Integrate IPs and develop logic for subsystems Understand and review subsystem architecture Develop microarchitecture specifications Review verification test plans Help debug and fix issues Work with performance analysis team to evaluate and improve system performance Understand incoming IPs, their...