Rtl állások, munkák Budapesten

• A vállalat kompenzációs stratégiájának támogatása és fejlesztése
• Bérpiaci benchmarkok, kompenzációs felmérések és iparági adatok elemzése
• Bérstruktúrák és bérsávok kialakítása, karbantartása és rendszeres felülvizsgálata

• SAP SuccessFactors modulok teljes körű bevezetésének vezetése (pl. Employee Central, Performance & Goals, Compensation, Recruiting, Learning, Onboarding, Payroll)
• Folyamatok feltérképezése és rendszerkövetelmények meghatározása

Use formal verification algorithms to formally prove the correctness of complicated logic problems Identify key behaviors for verification to write clear testplans for complex designs Implement testplans using innovative formal techniques Drive tools to realize their best performance Develop flow...

Contribute in SystemVerilog RTL verification and debug; formal bring-up of non-trivial IP blocks to achieve required quality levels (SystemVerilog/UVM, Formal, scripting) Work closely with engineers across design, performance modelling, validation, and implementation to meet all functional...

Review SoC solution architectures and develop micro-architecture specifications. Implement RTL designs, identify and fix bugs, perform design checks, generate power intent, and support implementation constraint creation. Collaborate with verification teams to review test plans and debug design...

Analyse and optimise the performance per watt of next generation solutions using innovative technologies, methodologies and tools Simulation, emulation, modelling and collaboration with cross-functional teams in design, verification, architecture, SW, and pre and post silicon test Build and...

Contribute to System IP microarchitecture specification and design Contribute in SystemVerilog, C and C++ to verification, modelling and debug to achieve required quality levels (SystemVerilog/UVM, C, C++, scripting) Propose and prototype new ways and define methodologies to reach goals more...

Be involved in System IP microarchitecture specification and design Participate in SystemVerilog RTL verification and debug; formal bring-up of non-trivial IP blocks to achieve required quality levels (SystemVerilog/UVM, Formal, scripting) Work closely with engineers across design, performance...