Python állás, munka

Contribute in SystemVerilog RTL verification and debug; formal bring-up of non-trivial IP blocks to achieve required quality levels (SystemVerilog/UVM, Formal, scripting) Work closely with engineers across design, performance modelling, validation, and implementation to meet all functional...

Review SoC solution architectures and develop micro-architecture specifications Implement RTL designs, identify and fix bugs, perform design checks, generate power intent, and support implementation constraint creation Collaborate with verification teams to review test plans and debug design issues...